Tracking Detector FLT
The processing of data from the CTD and the FTD will be integrated at the output stage of the tracking FLT. The RBOX is responsible for this. Chapter Eight describes how performance benefits may be obtained by extending track-finding methods to use data from both of the tracking detectors. It is likely for financial reasons that there will be some staging of detector readout and trigger electronics. For this reason, the RBOX is able to run separately the two tracking detector standalone triggers which are described here.
There are four types of readout module in the CTDFLT: cell processors for SL1, SL3 and SL5 (CP1, CP3, CP5) and sector processors (SP).
Measurement of the z-coordinate is central to the CTDFLT, the principle of which is shown in figure 5.1.
Figure 5.1: Principle of the CTDFLT.
5.2.1 Cell Processors
The z-by-timing value (see section 126.96.36.199) from the FADC is converted to a z/r bin number before input to the CPs. This is a fairly simple operation (because the radius is constant for a given SL) which is carried out by PROMs on the z-by-timing cards.
The CPs work with these values because straight tracks at constant polar angle will produce several hits in the same z/r bin. This means it is relatively straightforward to perform pattern recognition in this space to find such tracks.
Pairs of cells are read out by each CP because the tilt of the cells means that straight tracks from the origin will pass through two cells. The CPs search for patterns of hits at the same z/r. This pattern recognition logic is implemented in two stages consisting of RAM look-up tables and Xilinx field programmable gate array (FPGA) chips which are also used in the GFLTB. Xilinx chips allow logical networks of great complexity to be defined. Their most important property is that the networks may be reconfigured in the light of new requirements.
The input stages of the CP1 boards consider hits arriving within a short time-span of each other in an 8 x 32 bit table. The eight bits represent the layer number within SL1 and 32 bits is the division into z/r for this SL. Due to hardware constraints, the entire table cannot be processed simultaneously but instead is considered in a 4 x 8 bit window. This window is stepped along the 32 bit length of the table. Each window is further subdivided into an upper and lower half of 4 x 4 bits. For each half, a 64k x 4 RAM produces four bits from the input z/r pattern:
The first bit is set if hits are found consistent with a track from the vertex and the center bit is set if the hits were mostly in the middle two bins of the 4-bin half-window (this reduces the frequency with which the same track sets bits in two CPs). If wires are missing in a sequence of hits they may still be formed into a straight line from the interaction point but it is desirable to accord such a pattern less significance than one which has all wires hit. The pattern weight is a measure of this significance.
Analogous processes take place in CP3 and CP5 boards but here only four wires in a cell are instrumented for z-by-timing.
A hit pattern in a cell consistent with the hits being part of a good track is called a track segment. The CPs form a 31-bit word which is a z/r bitmap. This indicates whether or not candidate segments have been found in that particular z/r bin and is sent to the relevant SP.
5.2.2 Sector Processors
There are thirty-two SPs corresponding to the number of cells in SL1. Because tracks curve in the magnetic field, more than one CP in the larger radius SLs sends data to a SP. In fact, four CP3s and six CP5s are ‘OR’ed together to constitute a single trigger sector, as shown in figure 5.2.
Figure 5.2: One of the 32 trigger sectors of the CTDFLT.
Tracks from the interaction region which have a polar angle of greater than approximately 26° will cross all three instrumented SLs.
Assuming that there are no inefficiencies, this would mean that three segments would be found by the CPs. Each SP proceeds by trying to match segments. If the line joining segments in SL5 and SL1 points to the vertex to within some cut, and also passes through SL3 within +/-1 bin of a segment there, then a good track has been found.
Six bits allow for communication from each SP to the RBOX, which must combine information from all sectors to produce a decision for the CTDFLT as a whole. These six bits consist of three track bits and three vertex bits. The vertex bits come from processing in rz and the track bits come from r-φ processing.
If in a particular sector a good track has been found as described above, then the SL5 vertex bit is set. This indicates that successful extrapolation of at least one SL1 segment out to SL5, including a SL3 segment, to find a combined track which points to the vertex has taken place.
However, it is possible that the SL5 segment is not found, if for instance the track has a polar angle such that it leaves the CTD before reaching SL5. In this case it is still possible to do track-finding by combining segments in SL1 and SL3 only. The SL3 vertex bit is set if extrapolation is successful to this extent. If the rz processing in SL1 finds a segment, the SL1 vertex bit is set.
The three track bits, on the other hand, are measures of activity which has been formed into a track by the relevant CP but which may or may not have come from the vertex. The SL1 track bit indicates that there were sufficient hits in the CP1 in a sector for it to be able to form a track segment. If in addition this was true in one of the CP3s assigned to this sector, then the SL3 track bit is set. Finally, if all three instrumented SLs contain track segments then the SL5 track bit is set.
It is thus to be expected that a single good track within the θ region covered by all instrumented SLs will set all three vertex bits. A real event will of course usually contain more than one track and it is likely that some of these will be due to secondary interactions which will have origins distinct from the interaction region. A decision must be made in the RBOX as to what extent the event looks as if it consists of a minimum number of tracks coming from the interaction region – clearly a description satisfied by a good physics event.
The CTDFLT decision is made by the formation of a ratio; this is the central idea of all the tracking detector triggers. Ratios are formed representing how closely the event conforms to the hypothesis that it emanates from the interaction region and a cut is made on this ratio in order to reject background. The value of the cut is a tunable parameter and has very great influence in the optimization of the particular trigger.
It is the purpose of the three track bits from each SP to permit such a ratio to be formed. The numerator will be a function of the vertex bits, of which large numbers will be set by a good event. The denominator is a function of the track bits which are a measure of activity in the detector. If the ratio is high this means that a large proportion of activity in the detector is associated with good found tracks and the event may be triggered on with some confidence.
There is much overlap of information relating to the same tracks between different CPs and SPs which therefore need to have a high degree of connectivity. The 16 crates in the whole system, each of which contains the track-finding and z-by-timing boards for two trigger sections, are linked together in a circle so that data from adjacent trigger sectors is available to the processors.
All crates use a customized back-plane which concentrates readout bus lines, system control, timing and power supply in the bottom third allowing up to 300 interconnections to be made between cards.
The RBOX forms several ratios in its processing to produce a final CTDFLT decision which is based on two cuts. Firstly it finds the number of sectors which have their SL5 vertex bits set. It divides by the number of sectors which have their SL5 track bit set.
If the ratio so formed is greater than a cut then the event is accepted. In the simulation this cut is presently set to be 10%. An accepted event is labeled class two in the case of the CTD. If the ratio is less than the cut value but there are nevertheless more than two segments in SL5 then the event is rejected (class one).
For events which fall into neither of the above two classes, the SL1 data is utilized. If the ratio of sectors with their SL1 track bits set divided by the number with vertex bits set is greater than a cut, then the event is placed in class three. This cut is now set at 25%. These are quite possibly good events but one will have less confidence in accepting them. At present these events are simply added to the class twos in order to boost physics acceptance but it is important to remember that scope exists to treat them differently. For example the class threes might be required to fulfill more stringent conditions at later stages of processing.
The possibility exists to introduce a similar procedure for SL3 segments but studies so far have not looked at this question in sufficient detail to prove the necessity to do this. An additional class of accepted events could thus be provided for.
If the event has failed to be classified so far, then an assessment is made of its information content: if it has any segments in SL1 then it is rejected. If this is not the case, there is insufficient information for the processors to work with and the event is classified zero or ‘no decision’. Table 5.1 shows the classes and figure 5.3 shows diagrammatically how they are arrived at.
Table 5.1: Summary of CTDFLT event classifications.
Figure 5.3: CTDFLT event classification flowchart.
Other elements of the system are related to timing considerations. Since the drift times are longer than the beam crossing interval, the CTD will contain ionization from more than one crossing at any given moment. It is necessary to consider the arrival times of pulses in order to assign them to a beam crossing. Each crate contains a Local Timing Controller (LTC), each of which is connected to a separate Master Timing Controller (MTC) which receives clock signals from the GFLTB. In this way, the LTCs make a time signal in 48 ns bins available on each crate.
The CPs have logic designed to recognize patterns and sequences of hits so as to identify the crossing which produced the trigger. A mis-identification would result in a 96 ns difference between measured and real drift times for hits which would produce easily recognizable effects on segments as shown in figure 5.4.
Figure 5.4: Effect of crossing mis-identification on segments and maximum difference in drift times on adjacent sense wires.
An arrival time circuit (ATC) works in parallel with the pattern recognition. This generates two flags – ‘new’ and ‘valid’. The ATC works in 48 ns time-bins (i.e. two per beam crossing) and the new flag is set if a hit arrives which was preceded by three empty bins. This can be regarded as the first hit of a new event, as shown in the same figure. The maximum difference in arrival time of hits from the same track on adjacent sense wires occurs if the track passes through a wire and is given by Δt = d/vd where d is the separation between sense wires, equal to 8 mm x cos φ, φ is the angle of the track with respect to the sense wires and vd is the drift velocity. Using the nominal drift velocity of 50 microns per ns this means that Δt = 160 ns with φ = 90°. This is more than the three bin (48 ns x 3 = 144 ns) gap requirement. However, φ will not approach 90° but will be closer to 45° for tracks from the interaction point. It follows from this that the maximum gap permitted in a sequence of hits is two bins if they are to all be considered a part of the same event.
The maximum drift time covers ten bins and so the valid flag is set ten bins after the new flag was raised and remains up for one time-bin or until the last hit in the sequence arrives. The flag is sent directly to the output stage of the CPs.
The Forward Tracking Detector First Level Trigger (FTDFLT) is based on the same principle as the CTDFLT: straight tracks from the interaction region are again searched for. However the different geometry of the two detectors means that different logic is necessary to achieve this.
As described in section 3.3.1, the FTD has three sub-chambers each containing planes of wires with 60° relative offsets. These planes are known as u, v or w-layers depending on their orientation. The planes contain a large number of wires which cannot be used individually in the trigger because of hardware constraints. For example, the number of connections which may be made to a single electronic readout board is a limiting factor. It is necessary to OR wire signals together in such a way as to retain sufficient resolution to leave the FLT efficiency unimpaired.
The concept of diamonds, was developed to represent an optimal method of combining cells. Two of the three planes in an FTD sub-chamber are used to define a hit location, simply by ‘AND’ing the hits together. These must then be confirmed by a further hit cell in the third plane. This third cell is not required to be exactly in coincidence with the first two: the precision of the match is a parameter which may be adjusted in order to optimize performance. At the moment, it is envisaged that either the central cell in the third layer or either of the two adjacent cells may confirm a diamond. Figure 5.5 shows the method of forming diamonds.
Figure 5.5: Method of diamond forming to confirm three-dimensional hits.
A cell numbering convention has been defined whereby for good three-dimensional combinations, the sum of hit cells will be zero. There is a further combination of diamonds into super-diamonds in the outer regions. Near the beam-pipe where high resolution is required, the processing to find hit diamonds proceeds exactly as described. However, further out, they are combined into larger entities composed of 2 x 2 standard diamonds. At the largest radii, a super-diamond contains nine standard diamonds.
For financial reasons, only FTD sub-chambers one and three will be instrumented with diamond logic. It can be seen by similar triangles (figure 5.6) that if a pair of super-diamonds found in the two detectors lie on the same straight track from the interaction region, then their coordinates are related by equation 5.1.
Figure 5.6: Principle of the FTDFLT.
Conversely, tracks emanating from upstream of the interaction region will fail to satisfy this relationship by an amount which increases proportionally to their distance from the nominal interaction point.
The wire planes are orthogonal to the z-axis, and the u, v and w-layers are separated by 5 cm in z. In principle it would be necessary to examine how layers have been used to form a super-diamond. However it has been shown that in fact this small correction is not significant. It is therefore assumed that the same z-coordinate is obtained everywhere in a sub-chamber and so this reduces to a simple factor which can be applied to the radius of a hit super-diamond in FTD1 to predict the radius of a matching super-diamond. For infinite momentum tracks, the coordinate should be the same for both super-diamonds.
These principles form the basis on which the FTDFLT works. It attempts to match super-diamonds from FTD1 with those from FTD3. In the ideal case, all super-diamonds in a good event will be matched. In practice, some super-diamonds will fail to be matched because of inefficiencies and interactions etc. The FTDFLT finds the ratio of super-diamonds in FTD1 which have been matched with FTD3 super-diamonds divided by the total number of FTD1 super-diamonds and makes a cut on this quantity.
This is a valid approach since beam-gas events have fewer tracks coming from the interaction region, and hence will have less correlation of super-diamonds between the two sub-detectors.
Figure 5.7 shows the hardware design for the FTDFLT. The chamber will be readout by FADCs as described in section 3.3.1. These are interfaced via a discriminated post-amp signal to cell-hit boards (CHBs) which produce hit wire numbers. Each CHB should be able to contain logic units able to read out 32 cells. This means that a total of 16 CHBs, fitting into a single crate, will suffice for the FLT readout of FTD1 and FTD3. As shown in the diagram, this CHB crate has three fan-outs linked to two fan-ins on the second crate. The second crate contains six Sextant Boards (SBs) and six Segment Builder Modules (SBMs). This subdivision is a consequence of the FTD geometry.
The SBM and CHB electronics will rely on Xilinx FDGAs for logic implemented by look-up tables. These chips will be reprogrammable by the ROC. The CHBs will define hit cells by requiring a minimum number of hit wires out of the six in a cell.
Figure 5.7: Outline of two-crate FTDFLT hardware design.
The SB logic will form super-diamonds from hit cells and then apply coincidence logic to search for tracks from the interaction region in the manner previously described.
Finally the SBMs use hit and coincident diamonds to from the ratio for the FTDFLT decision and also to prepare for matching with CTD data.
Timing considerations are as important in the FTD as in the CTD since the FTD also contains ionization from more than one crossing at any given moment. A five bit shift register is connected to each wire-hit with each bit corresponding to a beam-crossing interval. An OR of the last four bits is fed into the CHB so that each hit remains valid over sufficient time such that all hits pertaining to a particular event will at some point be considered together.
Finally, the Readout-Controllers (ROCs) are responsible for sending information concerning the status of the FTDFLT to RC and the EVB, for handling of test data, and for reading out the contents of registers etc. for diagnosing trigger performance.